843004AGI-01

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 11, 2005

7

Integrated

Circuit

Systems, Inc.

ICS843004I-01

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843004I-01 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

10

Ω

V

CCA

10

µF

.01

µF

3.3V or 2.5V

.01

µF

V

CC

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical termi-

nation for LVPECL outputs. The two different layouts men-

tioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

designed to drive 50

Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating

frequency and minimize signal distortion.

Figures 2A and

2B show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist

and it would be recommended that the board designers

simulate to guarantee compatibility across all printed cir-

cuit and clock component process variations.