843002AGI-01

www.icst.com/products/hiperclocks.html

REV. A JANUARY 6, 2006

8

Integrated

Circuit

Systems, Inc.

ICS843002I-01

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical ter-

mination for LVPECL outputs. The two different layouts

mentioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs

that generate ECL/LVPECL compatible outputs. There-

fore, terminating resistors (DC current path to ground)

or current sources must be used for functionality. These

outputs are designed to drive 50

Ω transmission lines.

Matched impedance techniques should be used to maxi-

mize operating frequency and minimize signal distor-

tion. Figures 3A and 3B show two different layouts which

are recommended only as guidelines. Other suitable

clock layouts may exist and it would be recommended

that the board designers simulate to guarantee com-

patibility across all printed circuit and clock component

process variations.

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating.

Though not required, but for additional protection, a 1k

Ω

resistor can be tied from XTAL_IN to ground.

For applications not requiring the use of the reference clock,

it can be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the REF_CLK to

ground.

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

All unused LVPECL outputs can be left floating. We

recommend that there is no trace attached. Both sides of the

differential output pair should either be left floating or

terminated.