ICS843034 datasheet(3/23 Pages) ICST

3 / 23 page

843034AY

www.icst.com/products/hiperclocks.html

REV. A JULY 25, 2005

Integrated

Circuit

Systems, Inc.

ICS843034

FEMTOCLOCKS™

MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

PRELIMINARY

The TEST output is LOW when operating in the parallel input

mode. The relationship between the VCO frequency, the crystal

frequency and the M divider is defined as follows:

The M value and the required values of M0 through M8 are shown

in Table 3B to program the VCO Frequency Function Table.

Valid M values for which the PLL will achieve lock for a 25MHz

reference are defined as 23

≤ M ≤ 30.The frequency out is de-

fined as follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the

shift register are loaded into the M divider and Nx output di-

vider when S_LOAD transitions from LOW-to-HIGH. The M

divide and Nx output divide values are latched on the HIGH-

to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data

at the S_DATA input is passed directly to the M divider and Nx

output divider on each rising edge of S_CLOCK. The serial

mode can be used to program the M and Nx bits and test bits

T1 and T0. The internal registers T0 and T1 determine the state

of the TEST output as follows:

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes op-

eration using a 25MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the In-

put Frequency Characteristics, Table 5, NOTE 1.

The ICS843034 features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A fundamental crystal is used as the input to the on-

chip oscillator. The output of the oscillator is fed into the phase

detector. A 25MHz crystal provides a 25MHz phase detector

reference frequency. The VCO of the PLL operates over a

range of 560MHz to 750MHz. The output of the M divider is

also applied to the phase detector.

The phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock. The output of the

VCO is scaled by a divider prior to being sent to each of the LVPECL

output buffers. The divider provides a 50% output duty cycle.

The ICS843034 supports either serial or parallel programming

modes to program the M feedback divider and N output divider.

Figure 1 shows the timing diagram for each mode. In parallel

mode, the nP_LOAD input is initially LOW. The data on the M,

NA, and NB inputs are passed directly to the M divider and both

N output dividers. On the LOW-to-HIGH transition of the

nP_LOAD input, the data is latched and the M and N dividers

remain loaded until the next LOW transition on nP_LOAD or

until a serial event occurs. As a result, the M and Nx bits can be

hardwired to set the M divider and Nx output divider to a spe-

cific default state that will automatically occur during power-up.

TEST Output

LOW

S_Data, Shift Register Output

Output of M divider

FOUTA0 same frequency

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

T 1

NB2

NB1 NB0

NA2

NA1

NA0

M 0

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, NA0:NA2, NB0:NB2

nP_LOAD

S_LOAD

fVCO = fxtal x M

SERIAL LOADING

PARALLEL LOADING

M, N

Time

FOUT = fVCO = fxtal x M

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