PCF8545ATT datasheet(40/53 Pages) NXP

40 / 53 page

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

15 Application information

15.1 Power-on Reset

The built-in POR block acts on the rising edge of the VDD supply voltage. Depending

on the VDD rising edge in the application, the POR may not work properly. Therefore to

ensure proper device operation it is required to send nine clock pulses immediately after

power-on (see also UM10204).

15.2 I2C acknowledge after power-on

If the bus does not show an acknowledge at the first access, the command should be

sent a second time.

15.3 Resistors on I/O pins

The pin PORE comprises an internal, latching pull-down device, which keeps the input at

a low potential when left open. If the input is supposed to be at logic 0 potential, this pin

can be either connected to VSS or left open.

In case the pin is supposed to be at logic 1 potential, it must be connected to VDD to

avoid any cross-current during power-up. A series resistance between VDD and PORE

must not exceed 1 kΩ to ensure proper functionality.

16 Test information

16.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

PCA8551

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 3 May 2021

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PCF8545ATT датащи(PDF) 40 Page - NXP Semiconductors