843002AGI

www.icst.com/products/hiperclocks.html

REV. A JANUARY 4, 2006

8

Integrated

Circuit

Systems, Inc.

ICS843002I

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843002I provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01μF bypass

capacitor should be connected to each V

tor can also be replaced by a ferrite bead.

10

Ω

V

CCA

10

μF

.01

μF

3.3V or 2.5V

.01

μF

V

CC

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating.

Though not required, but for additional protection, a 1k

Ω

resistor can be tied from XTAL_IN to ground.

For applications not requiring the use of the reference clock,

it can be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the REF_CLK to

ground.

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

All unused LVPECL outputs can be left floating. We

recommend that there is no trace attached. Both sides of the

differential output pair should either be left floating or

terminated.