Integrated

Circuit

Systems, Inc.

840004AGI

www.icst.com/products/hiperclocks.html

REV. A JUNE 28, 2005

9

ICS840004I

PRELIMINARY

The transistor count for ICS840004I is: 3085

θ

JA

VS

θθθθθ

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

98.0°C/W

88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Figure 3 shows a schematic example of the ICS840004I. An

example of LVCMOS termination is shown in this schematic.

Additional LVCMOS termination approaches are shown in the

LVCMOS Termination Application Note. In this example, an 18

pF parallel resonant 26.5625MHz crystal is used.The C1=22pF

and C2=22pF are recommended for frequency accuracy. For

different board layout, the C1 and C2 may be slightly adjusted

for optimizing frequency accuracy. 1K

Ω pullup or pulldown re-

sistors can be used for the logic control input pins.

R4

100

LVCMOS

Logic Control Input Examples

VDD

XTAL_OUT

VDDO=3.3V

C5

0.1u

VDD

Set Logic

Input to

'1'

VDD=3.3V

C3

10uF

Unused outputs can be left floating. There should be

no trace attached to unused outputs. Device

characterized and specification limits set with all

outputs terminated.

If not using the crystal input, it can be left

floating. For additional protection the XTAL_IN

pin can be tied to ground.

C4

0.01u

RU2

Not Install

VDD

To Logic

Input

pins

VDDO

Optional Termination

C6

0.1u

Zo = 50 Ohm

LVCMOS

XTAL_IN

X1

C1

22pF

RD1

Not Install

VDD

R2

10

R3

36

VDDA

U1

ICS840004i

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

F_SEL0

nc

nXTAL_SEL

TEST_CLK

OE

MR

nPLL_SEL

VDDA

nc

VDD

XTAL_OUT

XTAL_IN

GND

Q3

Q2

VDDO

F_SEL1

GND

Q0

Q1

To Logic

Input

pins

RD2

1K

RU1

1K

VDD

R5

100

C2

22pF

Set Logic

Input to

'0'

VDD

Zo = 50 Ohm