83940DY

www.icst.com/products/hiperclocks.html

REV. B JUNE 15, 2004

1

Integrated

Circuit

Systems, Inc.

ICS83940D

The ICS83940D is a low skew, 1-to-18 LVPECL-

to-LVCMOS/LVTTL Fanout Buffer and a member

of the HiPerClockS™family of High Performance

Clock Solutions from ICS. The ICS83940D has

two selectable clock inputs. The PCLK, nPCLK

pair can accept LVPECL, CML, or SSTL input levels. The

LVCMOS_CLK can accept LVCMOS or LVTTL input levels.

The low impedance LVCMOS/LVTTL outputs are designed to

drive 50

Ω series or parallel terminated transmission lines.

The ICS83940D is characterized at full 3.3V and 2.5V or mixed

3.3V core, 2.5V output operating supply modes. Guaranteed

output and par t-to-par t skew characteristics make the

ICS83940D ideal for those clock distribution applications

demanding well defined performance and repeatability.

• 18 LVCMOS/LVTTL outputs

• Selectable LVCMOS_CLK or LVPECL clock inputs

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• LVCMOS_CLK accepts the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 250MHz

• Output skew: 150ps (maximum)

• Part to part skew: 750ps (maximum)

• Additive phase jitter, RMS: < 0.03ps (typical)

• Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output

supply modes

• 0°C to 70°C ambient operating temperature

• Lead-Free package available

• Pin compatible with the MPC940L

HiPerClockS™

ICS

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Pacakge

Top View

Q0:Q17

CLK_SEL

PCLK

nPCLK

LVCMOS_CLK

0

1

32 31 30 29 28 27 26 25

9

10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Q6

Q7

Q8

Q9

Q10

Q11

GND

GND

GND

LVCMOS_CLK

CLK_SEL

PCLK

nPCLK

ICS83940D

18