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IMX6SDLIEC датащи(PDF) 49 Page - NXP Semiconductors

номер детали IMX6SDLIEC
подробное описание детали  i.MX 6Solo/6DualLite Applications Processors for Industrial Products
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производитель  NXP [NXP Semiconductors]
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Electrical Characteristics
i.MX 6Solo/6DualLite Applications Processors for Industrial Products, Rev. 9, 11/2018
NXP Semiconductors
49
4.9.1
Reset Timings Parameters
Figure 9 shows the reset timing and Table 35 lists the timing parameters.
Figure 9. Reset Timing Diagram
4.9.2
WDOG Reset Timing Parameters
Figure 10 shows the WDOG reset timing and Table 36 lists the timing parameters.
Figure 10. WDOG1_B Timing Diagram
NOTE
XTALOSC_RTC_XTALI is approximately 32 kHz.
XTALOSC_RTC_XTALI cycle is one period or approximately 30
μs.
NOTE
WDOG1_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the
IOMUXC chapter of the i.MX 6Solo/6DualLite Reference Manual
(IMX6SDLRM).
4.9.3
External Interface Module (EIM)
The following subsections provide information on the EIM. Maximum operating frequency for EIM data
transfer is 104 MHz. Two system clocks are used with the EIM:
•
ACLK_EIM_SLOW_CLK_ROOT is used to clock the EIM module.
The maximum frequency for CLK_EIM_SLOW_CLK_ROOT is 132 MHz.
•
ACLK_EXSC is also used when the EIM is in synchronous mode.
The maximum frequency for ACLK_EXSC is 104 MHz.
Table 35. Reset Timing Parameters
ID
Parameter
Min
Max
Unit
CC1
Duration of SRC_POR_B to be qualified as valid.
1
—
XTALOSC_RTC_XTALI cycle
Table 36. WDOG1_B Timing Parameters
ID
Parameter
Min
Max
Unit
CC3
Duration of WDOG1_B Assertion
1
—
XTALOSC_RTC_XTALI cycle
SRC_POR_B
CC1
(Input)
WDOG1_B
CC3
(Output)



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