ADUCM3027BCPZ-R7 datasheet(8/39 Pages) AD

8 / 39 page

ADuCM3027/ADuCM3029

Data Sheet

Rev. B | Page 8 of 39

SYSTEM CLOCKS

External Crystal Oscillator Specifications

Table 8.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LOW FREQUENCY EXTERNAL CRYSTAL

OSCILLATOR (LFXTAL)

Frequency

fLFXTAL

32,768

External Capacitance from

SYS_LFXTAL_IN Pin to Ground and

from SYS_LFXTAL_OUT Pin to Ground

CLFXTAL

External capacitors on SYS_LFXTAL_IN

and SYS_LFXTAL_OUT pins must be

selected considering the printed circuit

board (PCB) trace capacitance due to

routing

Crystal Equivalent Series Resistance

ESRLFXTAL

kΩ

HIGH FREQUENCY EXTERNAL CRYSTAL

OSCILLATOR (HFXTAL)

Frequency

fHFXTAL

MHz

External Capacitance from

SYS_HFXTAL_IN Pin to Ground and

from SYS_HFXTAL_OUT Pin to Ground

CHFXTAL

External capacitors on SYS_HFXTAL_IN

and SYS_HFXTAL_OUT pins must be

selected considering the PCB trace

capacitance due to routing

Crystal Equivalent Series Resistance

ESRHFXTAL

On-Chip RC Oscillator Specifications

Table 9.

Parameter

Symbol

Min

Typ

Max

Unit

LOW FREQUENCY RC OSCILLATOR (LFOSC)

Frequency

fLFOSC

30,800

32,768

34,407

HIGH FREQUENCY RC OSCILLATOR (HFOSC)

Frequency

fHFOSC

25.09

26.728

MHz

System Clocks and PLL Specifications

Table 10.

Parameter

Symbol

Min

Typ

Max

Unit

PLL SPECIFICATIONS

PLL Input Clock Frequency1

fPLLIN

MHz

PLL Output Clock Frequency2, 3

fPLLOUT

MHz

System Peripheral Clock (PCLK) Frequency

fPCLK

0.8125

MHz

Advanced High Performance Bus Clock (HCLK) Frequency

fHCLK

0.8125

MHz

1 The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC).

2 For the maximum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 16, PLL_DIV2 = 1 for PLL input clock = 26 MHz; and PLL_MSEL = 13, PLL_NSEL =

26, PLL_DIV2 = 1 for PLL input clock = 16 MHz.

3 For the minimum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 30, PLL_DIV2 = 0 for PLL input clock = 26 MHz; and PLL_MSEL = 8, PLL_NSEL = 30,

PLL_DIV2 = 0 for 16 MHz.

ADUCM3027BCPZ-R7 датащи(PDF) 8 Page - Analog Devices

ADUCM3027BCPZ-R7 датащи(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

датащи скачать

ссылки URL