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ADUCM3027BCBZ-R7 датащи(PDF) 12 Page - Analog Devices

номер детали ADUCM3027BCBZ-R7
подробное описание детали  Ultra Low Power Arm Cortex-M3 MCU with Integrated Power Management
PDF  39 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADUCM3027BCBZ-R7 датащи(HTML) 12 Page - Analog Devices

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ADuCM3027/ADuCM3029
Data Sheet
Rev. B | Page 12 of 39
SPI Timing
Table 13.
Parameter1
Symbol
Min
Typ
Max
Unit
SPI MASTER MODE TIMING
Timing Requirements
Chip Select (CS) to Serial Clock (SCLK) Edge
tCS
(0.5 × tPCLK) − 3
ns
SCLK Low Pulse Width
tSL
tPCLK − 3.5
ns
SCLK High Pulse Width
tSH
tPCLK − 3.5
ns
Data Input Setup Time Before SCLK Edge
tDSU
5
ns
Data Input Hold Time After SCLK Edge
tDHD
20
ns
Switching Characteristics
Data Output Valid After SCLK Edge
tDAV
25
ns
Data Output Setup Before SCLK Edge
tDOSU
tPCLK − 2.2
ns
CS High After SCLK Edge
tSFS
(0.5 × tPCLK) − 3
ns
SPI SLAVE MODE TIMING
Timing Requirements
CS to SCLK Edge
tCS
38.5
ns
SCLK Low Pulse Width
tSL
38.5
ns
SCLK High Pulse Width
tSH
38.5
ns
Data Input Setup Time Before SCLK Edge
tDSU
6
ns
Data Input Hold Time After SCLK Edge
tDHD
8
ns
Switching Characteristics
Data Output Valid After SCLK Edge
tDAV
20
ns
Data Output Valid After CS Edge
tDOCS
20
ns
CS High After SCLK Edge
tSFS
38.5
ns
1 These specifications are characterized with respect to double drive strength.
CS
MOSI
MSB
MSB IN
BIT 6 TO BIT 1
LSB
LSB IN
BIT 6 TO BIT 1
MISO
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
tCS
tSFS
tSH
tDAV
tDSU
tDHD
tSL
Figure 8. SPI Master Mode Timing (Phase Mode = 1)



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