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DA9141

High-Performance, 25 A/40 A Peak, DC-DC Converter

Datasheet

Revision 1.6

25-Aug-2021

CFR0011-120-00

21 of 46

5.4

I2C Communication

All features of DA9141 can be controlled with the I2C interface, which is enabled or disabled as an

OTP setting.

I2C

Description

Disabled

SCL/GPIO3 and SDA/GPIO4 pins can be used as

GPIO

Enabled

SCL/GPIO3 and SDA/GPIO4 pins are used as I2C

clock input and I2C data input/output.

GPIO3 functions as the I2C clock (SCL) and GPIO4 carries all the power manager bidirectional I2C

data (SDA). The I2C interface is open drain supporting multiple devices on a single line. The bus lines

have to be pulled high by external pull-up resistors (2

kΩ to 20 kΩ). The standard frequency of the

I2C bus is 1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

5.4.1

I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven

towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has

settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the

receiver’s shift register.

A two-byte serial protocol is used containing one byte for address and one byte for data. Data and

address transfer are transmitted MSB first for both read and write operations. All transmissions begin

with the START condition from the master while the bus is in idle state (the bus is free). It is initiated

by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is

indicated by a low to high transition on the SDA line while the SCL is in the high state).

SCL

SDA

Figure 6: I2C START and STOP Condition Timing

The I2C bus is monitored for a valid slave address whenever the interface is enabled. It responds

immediately when it receives its own slave address. The acknowledge is done by pulling the SDA

line low during the following clock cycle (white blocks marked with A in Figure 7 and Figure 8).

The protocol for a register write from master to slave consists of a START condition, a slave address

with read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a

STOP condition. DA9141 responds to all bytes with acknowledge (A), see Figure 7.

SLAVEadr

REGadr

DATA

S = START condition

A = Acknowledge (low)

P = STOP condition

W = Write (low)

Master to Slave

Slave to Master

7-bits

1-bit

8-bits

Figure 7: I2C Byte Write (SDA Line)

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