ICS650-01B

System Peripheral Clock Source

MDS 650-01B A

2

Revision 041499

Printed 11/15/00

Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax

Pin #

Name

Type

Description

1

BSEL

I

BCLK1 and BCLK2 Select pin. Determines frequency of B clocks per table above.

2

X2

XO

Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.

3

X1

XI

Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.

4

VDD

P

Connect to VDD. Must be same value as other VDD. Decouple with pin 6.

5

GND

P

Connect to ground.

6

GND

P

Connect to ground.

7

BCLK1

O

BCLK1 output. Determined by BSEL pin per table above.

8

BCLK2

O

BCLK2 output. Determined by BSEL pin per table above. Only clock active if PSEL1, 0=1.

9

ACLK

O

AC97 Audio clock output per table above.

10

PCLK4

O

PCLK output number 4 per table above.

11

OE

I

Output Enable. Tri-states all outputs when low.

12

PCLK1

O

PCLK output number 1 per table above.

13

14.318M

O

14.31818 MHz buffered reference clock output.

14

GND

P

Connect to ground.

15

ASEL

I

ACLK Select pin. Determines frequency of Audio clock per table above.

16

VDD

P

Connect to VDD. Must be same value as other VDD. Decouple with pin 14.

17

PCLK3

O

PCLK output number 3 per table above.

18

PCLK2

O

PCLK output number 2 per table above.

19

PSEL0

I

Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.

20

PSEL1

I

Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.

Pin Descriptions

Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection

1

16

2

3

4

15

14

13

VDD

ACLK

X2

VDD

20 pin (150 mil) SSOP

5

6

7

8

12

11

10

9

PCLK4

PSEL0

X1

BSEL

PCLK2

PSEL1

PCLK3

PCLK1

OE

BCLK2

BCLK1

18

17

19

20

GND

GND

14.318M

GND

ASEL

PSEL1

PSEL0

PCLK1

PCLK2,3

PCLK4

0

0

25.00

50.00

18.75

0

M

TEST

TEST

TEST

0

1

TEST

TEST

TEST

M

0

40.00

80.00

20.00

M

M

33.3334

66.6667

25.00

M

1

20.00

40.00

25.00

1

0

20.00

33.3334

25.00

1

M

20.00

66.6667

25.00

1

1

Stops low all cloocks except BCL

LK2.

Processor Clock (MHz)

BSEL

BCLK1

BCLK2

0

3.688

4.917

M50

25

180

40

Audio Clock (MHz)

B Clocks (MHz)

0 = connect directly to ground, 1 = connect directly

to VDD, M=leave unconnected (floating)

Pin Assignment

ASEL

ACLK

0

49.152

M

24.576

1

12.288