843AG-106

www.icst.com/products/hiperclocks.html

REV. A JANUARY 10, 2006

7

Integrated

Circuit

Systems, Inc.

ICS843-106

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, termi-

nating resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

drive 50

Ω transmission lines.Matched impedance techniques

should be used to maximize operating frequency and mini-

mize signal distortion. Figures 2A and 2B show two different

layouts which are recommended only as guidelines. Other

suitable clock layouts may exist and it would be recommended

that the board designers simulate to guarantee compatibility

across all printed circuit and clock component process varia-

tions.

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The table shown provides a basic guideline in selecting

the proper quartz crystal that meets a timing budget of

±100ppm. For more information on selecting the proper

r

e

t

e

m

a

r

a

Pl

a

c

i

p

y

Ts

t

i

n

U

e

c

n

a

r

e

l

o

T

y

c

n

e

u

q

e

r

F

0

3

±

m

p

p

y

t

il

i

b

a

t

S

y

c

n

e

u

q

e

r

F

0

3

±

m

p

p

s

r

a

e

Y

0

1

r

o

f

g

n

i

g

A5

1

±m

p

p

r

o

t

a

ll

i

c

s

O

S

C

I

f

o

y

c

a

r

u

c

c

A0

1

±m

p

p

y

c

a

r

u

c

c

A

e

c

n

a

t

i

c

a

p

a

C

d

a

o

L3

±m

p

p

r

o

r

r

E

g

n

i

m

i

T

l

l

a

r

e

v

O

l

a

t

o

T

8

8

±m

p

p

crystal, see the application note, Crystal Timing Budget

and Accuracy for FemtoClock™ .