AD9517-2ASLASHPCBZ datasheet(35/80 Pages) AD

35 / 80 page

Data Sheet

AD9517-2

Rev. F | Page 35 of 80

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by a

single-ended signal, the unused side (REFIN) should be

decoupled via a suitable capacitor to a quiet ground. Figure 49

shows the equivalent circuit of REFIN.

REF1

REF2

REFIN

150Ω

10kΩ

12kΩ

10kΩ

REFIN

85kΩ

Figure 49. REFIN Equivalent Circuit

Reference Switchover

The AD9517 supports dual single-ended CMOS inputs, as well

as a single differential reference input. In the dual single-ended

reference mode, the AD9517 supports automatic and manual

PLL reference clock switching between REF1 (on Pin REFIN)

and REF2 (on Pin REFIN). This feature supports networking

and other applications that require smooth switching of redundant

references. When used in conjunction with the automatic holdover

function, the AD9517 can achieve a worst-case reference input

switchover with an output frequency disturbance as low as 10

ppm.

When using reference switchover, the single-ended reference

inputs should be dc-coupled CMOS levels and never be allowed

to go to high impedance. If these inputs are allowed to go to high

impedance, noise may cause the buffer to chatter, causing a

false detection of the presence of a reference.

Reference switchover can be performed manually or auto-

matically. Manual switchover is performed either through

requires the presence of a clock on the reference input that is being

switched to, or that the deglitching feature be disabled (Register

0x01C[7]). The reference switching logic fails if this condition

is not met, and the PLL does not reacquire.

Automatic revertive switchover relies on the REFMON pin to

indicate when REF1 disappears. By programming Register 0x01B =

0xF7 and Register 0x01C = 0x26, the REFMON pin is

programmed to be high when REF1 is invalid, which commands

the switch to REF2. When REF1 is valid again, the REFMON

pin goes low, and the part again locks to REF1. It is also possible to

use the STATUS pin for this function, and REF2 can be used as

the preferred reference.

A switchover deglitch feature ensures that the PLL does not

receive rising edges that are far out of alignment with the newly

selected reference.

Automatic nonrevertive switching is not supported.

Reference Divider R

The reference inputs are routed to the reference divider, R.

R (a 14-bit counter) can be set to any value from 0 to 16383

by writing to Register 0x011 and Register 0x012. (Both R = 0 and

R = 1 give divide-by-1.) The output of the R divider goes to one

of the PFD inputs to be compared to the VCO frequency

divided by the N divider. The frequency applied to the PFD

must not exceed the maximum allowable frequency, which

depends on the antibacklash pulse setting (see Table 2).

The R counter has its own reset. R counter can be reset using

the shared reset bit of the R, A, and B counters. It can also be

reset by a SYNC operation.

VCXO/VCO Feedback Divider N—P, A, B, R

The N divider is a combination of a prescaler (P) and two

counters, A and B. The total divider value is

N = (P × B) + A

where the value of P can be 2, 4, 8, 16, or 32.

Prescaler

The prescaler of the AD9517 allows for two modes of

operation: a fixed divide (FD) mode of 1, 2, or 3, and dual

modulus (DM) mode where the prescaler divides by P and (P +

1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The

prescaler modes of operation are given in Table 54, Register

0x016[2:0]. Not all modes are available at all frequencies (see

Table 2).

When operating the AD9517 in dual modulus mode (P//P + 1),

the equation used to relate input reference frequency to VCO

output frequency is

fVCO = (fREF/R) × (P × B + A) = fREF × N/R

However, when operating the prescaler in an FD mode of 1,

2, or 3, the A counter is not used (A = 0) and the equation

simplifies to

fVCO = (fREF/R) × (P × B) = fREF × N/R

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,

in which case the previous equation also applies.

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