ICS1893AG datasheet(51/135 Pages) ICST

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Chapter 7 Functional Blocks

ICS1893AG, Rev. A 04/14/05

April, 2005

ICS1893AG Data Sheet - Preliminary

7.6 Functional Block: Management Interface

As part of the MAC/Repeater Interface, the ICS1893AG provides a two-wire serial management interface

which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used

to exchange control, status, and configuration information between a Station Management entity (STA) and

the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of

management registers. The ISO/IEC standard specifies the following components of this serial

management interface:

• A set of registers (Section 7.6.1, “Management Register Set Summary”)

• The frame structure (Section 7.6.2, “Management Frame Structure”)

• The protocol

In compliance with the ISO/IEC specification, the ICS1893AG implementation of the serial management

interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the

exchange of data. These pins remain active in all ICS1893AG MAC/Repeater Interface modes (that is, the

10/100 MII, 100M Symbol, and 10M Serial interface modes).

7.6.1 Management Register Set Summary

The ICS1893AG implements a Management Register set that adheres to the ISO/IEC standard. This

Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.

7.6.2 Management Frame Structure

The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the

exchange of configuration, control, and status data between a PHY, such as an ICS1893AG, and an STA.

All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange

data through a pre-defined register set.

The ICS1893AG complies with the ISO/IEC defined Management Frame Structure and protocol. This

structure supports both read and write operations. Table 7-2 summarizes the Management Frame

Structure.

Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE

periods are not part of the Management Frame Structure.

Table 7-2. Management Frame Structure Summary

Frame Field

Data

Comment

Acronym

Frame Function

PRE

Preamble (Bit 1.6)

11..11

32 ones

SFD

Start of Frame

2 bits

Operation Code

10/01 (read/write)

2 bits

PHYAD

PHY Address (Bits 16.10:6)

AAAAA

5 bits

REGAD

RRRRR

5 bits

Turnaround

Z0/10 (read/write)

2 bits

DATA

Data

DDD..DD

16 bits

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