Figure 6

VCO GAIN

MAX FREQUENCY

4

120 MHz

5

200 MHz

6

260 MHz

7*

*SPECIAL APPLICATION. Contact factory for custom product above

260 MHz.

•

Phase Detector Gain: For most graphics applications and

divider ranges, set P[1, 0] = 10 and set P[2] = 1. Under

some circumstances, setting the P[2] bit “on” can reduce

jitter. During 1562 operation at exact multiples of the

crystal frequency, P[2] bit = 0 may provide the best jitter

performance.

Board Test Support

It is often desirable to statically control the levels of the output

pins for circuit board test. The ICS1562B supports this through

a register programmable mode, AUXEN. When this mode is

set, two register bits directly control the logic levels of the

CLK+/CLK- pins and the LOAD pin. This mode is activated

when the S[0] and S[1] bits are both set to logic 1. See Register

Mapping for details.

Power Supplies and Decoupling

The ICS1562B has two VSS pins to reduce the effects of

package inductance. Both pins are connected to the same

potential on the die (the ground bus). BOTH of these pins

should connect to the ground plane of the video board as close

to the package as is possible.

The ICS1562B has a VDDO pin which is the supply of +5 volt

power to all output drivers. This pin should be connected to the

power plane (or bus) using standard high-frequency decou-

pling practice. That is, capacitors should have low series induc-

tance and be mounted close to the ICS1562B.

The VDD pin is the power supply pin for the PLL synthesizer

circuitry and other lower current digital functions. We recom-

mend that RC decoupling or zener regulation be provided for

this pin (as shown in the recommended application circuitry).

This will allow the PLL to “track” through power supply

fluctuations without visible effects. See Figure 6 for typical

external circuitry.

ICS1562B

6