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ICS348RIP датащи(PDF) 1 Page - Integrated Circuit Systems

номер детали ICS348RIP
подробное описание детали  Quad PLL Field Programmable VersaClock Synthesizer
PDF  7 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS348RIP датащи(HTML) 1 Page - Integrated Circuit Systems

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ICS348
MDS 348 H
1
Revision 051705
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Quad PLL Field Programmable VersaClock Synthesizer
Description
The ICS348 field programmable clock synthesizer
generates up to 9 high-quality, high-frequency clock
outputs including multiple reference clocks from a low
frequency crystal or clock input. The ICS348 has 4
independent on-chip PLLs and is designed to replace
crystals and crystal oscillators in most electronic
systems.
Using ICS’ VersaClockTM software to configure PLLs
and outputs, the ICS348 contains a One-Time
Programmable (OTP) ROM to allow field
programmability. Programming features include eight
selectable configuration registers, up to two sets of four
low-skew outputs.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
The ICS348 is also available in factory programmed
custom versions for high-volume applications.
Features
Packaged as 20-pin SSOP (QSOP)
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3V
Input crystal frequency of 5 to 27 MHz
Input clock frequency of 2 to 50 MHz
Up to nine reference outputs
Up to two sets of four low-skew outputs
Operating voltages of 3.3 V
Advanced, low power CMOS process
For one output clock, use the ICS341 (8-pin). For two
output clocks, use the ICS342 (8-pin). For three
output clocks, use the ICS343 (8-pin). For more than
three outputs, use the ICS345 or ICS348.
Available in Pb (lead) free packaging
Block Diagram
C rystal
O scillator
PLL1
GN D
2
3
VDD
PDT S
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
S2:S 0
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
3
OT P
RO M
with
PLL
Values
PLL4
X2
Cry stal or
cloc k input
E xternal capacitors are
required w ith a crystal input.
X 1/IC LK


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