SLG47502 datasheet(2/191 Pages) DIALOG

2 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

2 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Contents

General Description ................................................................................................................................................................. 1

Key Features............................................................................................................................................................................. 1

Applications.............................................................................................................................................................................. 1

1 Block Diagram ...................................................................................................................................................................... 7

2 Pinout .................................................................................................................................................................................... 8

2.1 Pin Configuration - STQFN- 12L ............................................................................................................................ 8

2.2 Pin Configuration - MSTQFN- 16L ......................................................................................................................... 9

3 Characteristics ...................................................................................................................................................................13

3.1 Absolute Maximum Ratings .................................................................................................................................13

3.2 Electrostatic Discharge Ratings ...........................................................................................................................13

3.3 Recommended Operating Conditions .................................................................................................................13

3.4 Electrical Characteristics ......................................................................................................................................14

3.5 I2C Pins Electrical Characteristics ........................................................................................................................16

3.6 Macrocells Current Consumption .........................................................................................................................18

3.7 Timing Characteristics ..........................................................................................................................................19

3.8 Counter/Delay Characteristics .............................................................................................................................21

3.9 Oscillator Characteristics .....................................................................................................................................21

3.10 ACMP Characteristics ........................................................................................................................................22

4 User Programmability ........................................................................................................................................................24

5 IO Pins .................................................................................................................................................................................25

5.1 GPIO Pins ............................................................................................................................................................25

5.2 GPI Pin .................................................................................................................................................................25

5.3 Pull-Up/Down Resistors .......................................................................................................................................25

5.4 Fast Pull-up/down during Power-up .....................................................................................................................25

5.5 GPI Structure .......................................................................................................................................................26

5.6 GPIO with I2C Mode IO Structure ........................................................................................................................27

5.7 Matrix OE IO Structure .........................................................................................................................................28

5.8 IO Typical Performance .......................................................................................................................................29

6 Connection Matrix ..............................................................................................................................................................32

6.1 Matrix Input Table ...............................................................................................................................................33

6.2 Matrix Output Table ..............................................................................................................................................35

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................38

7 Combination Function Macrocells ....................................................................................................................................39

7.1 2-Bit LUT or D Flip-Flop or Shift Register Macrocells ..........................................................................................39

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................44

7.3 3-Bit LUT or D Flip-Flop with Set/Reset or Shift Register Macrocells ..................................................................46

7.4 4-Bit LUT or D Flip-Flop with Set/Reset or Shift Register Macrocell ....................................................................58

8 Multi-Function Macrocells .................................................................................................................................................62

8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................62

8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ..............................................................................71

8.3 CNT/DLY Timing Diagrams ..................................................................................................................................74

8.4 FSM Timing Diagrams .........................................................................................................................................81

8.5 Wake and Sleep Controller ..................................................................................................................................84

9 Analog Comparators ..........................................................................................................................................................89

9.1 ACMP0H Block Diagram ......................................................................................................................................90

9.2 ACMP1H Block Diagram ......................................................................................................................................91

9.3 ACMP Typical Performance .................................................................................................................................92

10 Programmable Delay/Edge Detector ..............................................................................................................................93

10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................93

11 Additional Logic Function. Deglitch Filter .....................................................................................................................94

12 Voltage Reference ............................................................................................................................................................95

12.1 Voltage Reference Overview .............................................................................................................................95

12.2 Vref Selection Table ...........................................................................................................................................95

12.3 Vref Block Diagram ...........................................................................................................................................96

12.4 Vref Typical Performance ...................................................................................................................................97

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