SLG46585 datasheet(2/210 Pages) DIALOG

2 / 210 page

Datasheet

18-Sep-2019

CFR0011-120-00

Revision 3.3

2 of 210

SLG46585

GreenPAK Programmable Mixed-Signal Matrix with Asynchronous

State Machine, LDOs, and DC/DC Converter

Contents

General Description ................................................................................................................................................................. 1

Key Features............................................................................................................................................................................. 1

Applications ............................................................................................................................................................................. 1

1 Block Diagram ....................................................................................................................................................................10

2 Pinout ..................................................................................................................................................................................11

2.1 Pin Configuration - MSTQFN- 29L ......................................................................................................................11

3 Characteristics ...................................................................................................................................................................15

3.1 Absolute Maximum Ratings .................................................................................................................................15

3.2 Electrostatic Discharge Ratings ...........................................................................................................................15

3.3 Recommended Operating Conditions .................................................................................................................15

3.4 Electrical Characteristics ......................................................................................................................................15

3.5 Timing Characteristics ..........................................................................................................................................27

3.6 OSC Characteristics .............................................................................................................................................30

3.7 Analog Comparator Characteristics .....................................................................................................................32

3.8 Low Drop Out “LDO” Regulator Electrical Characteristics ...................................................................................34

3.9 DC/DC Converter Electrical Characteristics .........................................................................................................36

4 User Programmability ........................................................................................................................................................38

5 IO Pins .................................................................................................................................................................................39

5.1 Input Modes .........................................................................................................................................................39

5.2 Output Modes .......................................................................................................................................................40

5.3 Pull-Up/Down Resistors .......................................................................................................................................40

5.4 IO Register Settings .............................................................................................................................................40

5.5 GPI Structure .......................................................................................................................................................44

5.6 Matrix OE IO Structure .........................................................................................................................................45

5.7 IO Structure ..........................................................................................................................................................47

6 Connection Matrix ..............................................................................................................................................................48

6.1 Matrix Input Table ...............................................................................................................................................49

6.2 Matrix Output Table .............................................................................................................................................51

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................54

6.4 Connection Matrix Virtual Outputs .......................................................................................................................54

7 Combination Function Macrocells ....................................................................................................................................55

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................55

7.2 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................59

7.3 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................67

7.4 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................71

7.5 CNT/DLY Timing Diagrams ..................................................................................................................................80

7.6 Wake and Sleep Controller ..................................................................................................................................87

8 Combinatorial Logic ...........................................................................................................................................................89

8.1 4-bit LUT with Two Outputs ..................................................................................................................................89

9 Analog Comparators ..........................................................................................................................................................91

9.1 ACMP0 Block Diagram and Register Settings .....................................................................................................92

9.2 ACMP1 Block Diagram and Register Settings .....................................................................................................94

9.3 ACMP2 Block Diagram and Register Settings .....................................................................................................96

9.4 ACMP3 Block Diagram and Register Settings .....................................................................................................98

9.5 ACMPs Typical Performance ............................................................................................................................. 100

10 Pipe Delay ....................................................................................................................................................................... 101

11 Programmable Delay/Edge Detector ............................................................................................................................ 101

11.1 Programmable Delay Timing Diagram - Edge Detector Output ...................................................................... 101

12 Additional Logic Functions ........................................................................................................................................... 103

12.1 Deglitch Filter/Edge Detector ........................................................................................................................... 103

13 RTC Binary Counter ....................................................................................................................................................... 104

13.1 RTC Binary Counter Shadow Buffer ................................................................................................................ 105

14 Voltage Reference .......................................................................................................................................................... 106

14.1 Voltage Reference Overview ........................................................................................................................... 106

14.2 Vref Selection Table ........................................................................................................................................ 106

15 Analog Temperature Sensor ......................................................................................................................................... 107

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