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PLL520-10DI датащи(PDF) 2 Page - PhaseLink Corporation |
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PLL520-10DI датащи(HTML) 2 Page - PhaseLink Corporation |
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2 / 8 page ![]() PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 FREQUENCY SELECTION TABLE Pad #28 SEL3 Pad #29 SEL2 Pad #19 SEL1 Pad #20 SEL0 Selected Multiplier 0 0 1 1 Fin x 8 1 0 1 1 Fin x 4 1 1 1 0 Fin x 2 1 1 1 1 No multiplication (no PLL) All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CX+ 2 Built-in Capacitance CX- 2 Inter-electrode capacitance C0 65MHz to 130 MHz (VDD=3.3V) 2.6 pF C0/C1 ratio (gamma) γ 350 - Oscillation Frequency OF Fund. 65 130 MHz |
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