PLL501-05/-07

VCXO Clock Generator IC

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/10/01 Page 5

6. External Components and Layout Recommendations

The PLL501-05/-07 requires a minimum number of external components for proper operation. A

standard low frequency decoupling capacitor of 2

µF or more should be used between VDD and GND

(pin 2 and pin 4, as well as pin 6 and pin 7). Additionally, higher frequency decoupling capacitors of

0.01

µF are required between VDD and GND (between pin 2 and 4, and between pin 6 and 7). These

higher frequency decoupling capacitors must be connected as close to the PLL501-05/-07 chip as

possible, and preferably directly next to the PLL501-05/-07 pins. A series termination resistor of 33

Ω

may be used for the clock output.

The input crystal must be connected as close to the chip as possible, and preferably directly next to the

PLL501-05/-07 pins.

GND, as close to the crystal as possible, and preferably directly next to the crystal electrodes. Consult

PhaseLink for recommended suppliers.