PCF8553 datasheet(34/51 Pages) NXP

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NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

aaa-012360

128

160

ffr (Hz)

IDD(LCD)

(μA)

(2)

(1)

(4)

(3)

(6)

(5)

(8)

(7)

Tamb = 25 °C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0, CL = 1.6 nF.

1. Static, all segments/elements off.

2. Static, all segments/elements on.

3. MUX 1:2, bias level 1⁄2, all segments/elements off.

4. MUX 1:2, bias level 1⁄2, all segments/elements on.

5. MUX 1:3, bias level 1⁄3, all segments/elements off.

6. MUX 1:3, bias level 1⁄3, all segments/elements on.

7. MUX 1:4, bias level 1⁄3, all segments/elements off.

8. MUX 1:4, bias level 1⁄3, all segments/elements on.

Figure 24. Typical IDD(LCD) as function of ffr

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FF[1:0] = 00

FF[1:0] = 01

FF[1:0] = 10

ffr

frame frequency

FF[1:0] = 11

128

fclk(int)

internal clock frequency

ffr = 64 Hz, nMUX = 4

[1] -

1024

fclk(ext)

external clock frequency

[1] -

4096

tclk(H)

HIGH-level clock time

external clock

µs

tclk(L)

LOW-level clock time

external clock

µs

tw(rst)

reset pulse width

on pin RST

µs

Table 18. Frequency characteristics

[1]

respectively (see Table 5 and Table 6).

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 April 2021

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