PLL650-09

Low Cost Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 09/19/02 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• 4 outputs fixed at 50MHz .

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTIONS

The PLL 650-09 is a low cost, low jitter, and high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, the chip

accepts 25.0 MHz crystal, and produces multiple output

clocks for networking chips.

PIN CONFIGURATION

BLOCK DIAGRAM

XTAL

OS C

50MHz

XIN

XOUT

Control

Logic

4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VDD

VDD

N/C

GND

GND

GND

VDD

50MHz

XIN

XOUT

GND

VDD

50MHz

GND

50MHz

50MHz