Preliminary

PLL601-03

Low Phase Noise PLL Clock Multiplier

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 06/15/01 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

CLK

1

O

Clock output from VCO. Equals the input frequency times multiplier.

REFEN

2

I

Reference clock enable. When Low, it turns off REFOUT.

VDD

3,4,5

P

3.3V Power Supply.

XIN

8

I

Crystal input to be connected to 10-30MHz fundamental parallel mode crys-

XOUT

6

O

Crystal Connection.

OE

12

I

Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up.

REFOUT

13

O

Buffered crystal oscillator clock output. Controlled by REFEN.

S0

11

I

Multiplier Select Pin 0. Determines CLK output. Has internal pull-up.

S1

7

I

Multiplier Select Pin 1. Determines CLK output. Has internal pull-up.

S2

9

I

Multiplier Select Pin 1. Determines CLK output. Has internal pull-up.

S3

10

I

Multiplier Select Pin 3. Determines CLK output. Has internal pull-up.

GND

14,15,16

P

Ground.