PLL520-80

Low Phase Noise VCXO (9.5-65MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page

3

4. General Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current (Loaded Outputs)

PECL/LVDS/CMOS

100/80/40

mA

Operating Voltage

2.97

3.63

V

Output Clock Duty Cycle

@ 1.25V (LVDS)

45

45

45

50

50

50

55

55

55

%

Short Circuit Current

±50

mA

5. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS at 27MHz

2.3

Period jitter peak-to-peak at 27MHz

With capacitive decoupling between

VDD and GND. Over 10,000 cycles

18.5

20

ps

Accumulated jitter RMS at 27MHz

2.3

Accumulated jitter peak-to-peak at 27MHz

With capacitive decoupling between

VDD and GND. Over 1,000,000

cycles.

24

25

ps

Random Jitter

“RJ” measured on Wavecrest SIA

3000

2.3

ps

Measured on Wavecrest SIA 3000

6. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

Phase Noise relative

to carrier

27MHz

-75

-100

-125

-140

-145

dBc/Hz

Note: Phase Noise measured on Agilent E5500

7. CMOS Output Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

30

mA

Output drive current

(High Drive)

30

mA

10

mA

Output drive current

(Standard Drive)

10

mA

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

ns