PLL620-30

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 11/09/04 Page 1

FEATURES

• 65MHz to 130MHz Crystal input.

• Output range: 32.5MHz – 130MHz (no PLL).

• Low Injection Power for crystal, 50uW.

• Complementary outputs: PECL or LVDS.

• Selectable OE Logic

• Supports 2.5V or 3.3V-Power Supply.

• Available in die form.

• Thickness 10 mil.

DESCRIPTION

The PLL620-30 is a XO IC specifically designed to

130MHz, with selectable PECL or LVDS outputs and

OE logic (enable high or enable low). Its design was

optimized to tolerate higher limits of interelectrode

capacitance and bonding capacitance to improve

yield. It achieves very low current into the crystal

resulting in better overall stability.

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

BLOCK DIAGRAM

DIE CONFIGURATION

OUTPUT SELECTION AND ENABLE

OUTSEL

(Pad #9)

Selected Output

0

LVDS

1

PECL (default)

OESEL

(Pad #25)

OE_CTRL

(Pad #30)

State

0

Tri-state

0

1

Output enabled (default)

0

Output enabled (default)

1 (default)

1

Tri-state

Pad #9, #25: Bond to GND to set to “0”. Internal pull up.

Pad #30: Logical states defined by PECL levels if OESEL is “1”

Logical states defined by CMOS levels if OESEL is “0”

OUTPUT FREQUENCY SELECTOR

S2

Output

0

Input/2

1(Default)*

Input

*Internally set to ‘Default’ through 60K pull-up resistor

18

19

20

21

23

25

7

13

10

26

29

31

Y

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

1

2

3

4

5

27

28

30

OUTSEL^

PECL

LVDS

VDDBUF

VDDBUF

PECLB

LVDSB

N/C

GNDBUF

XIN

XOUT

N/C

OE

CTRL

S2^

N/C

Die ID:

A2020-20A

C502A

XIN

XOUT

OE

Q

PLL620-30

Q

Oscillator

Amplifier