Preliminary for proposal

PLL602-41

Low Phase Noise CMOS XO (48MHz to 96MHz)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 07/13/01 Page 3

3. Jitter and Phase Noise specification

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

With capacitive decoupling

between VDD and GND.

VIN = 3.3V

TBM

ps

Accumulated jitter RMS

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

VIN = 3.3V

TBM

ps

Phase Noise relative to carrier

100Hz offset, VIN = 3.3V

-101

dBc/Hz

Phase Noise relative to carrier

1kHz offset, VIN = 3.3V

-127

dBc/Hz

Phase Noise relative to carrier

10kHz offset, VIN = 3.3V

-137

dBc/Hz

Phase Noise relative to carrier

100kHz offset, VIN = 3.3V

-137

dBc/Hz

4. DC Specification

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Operating Voltage

VDD

3.135

3.465

V

Input High Voltage

2

V

Input Low Voltage

0.8

V

Input High Voltage

For XIN pin

(VDD/2)

+ 1

VDD/2

V

Input Low Voltage

For XIN pin

VDD/2

(VDD/2)

− 1

V

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Output High Voltage At

CMOS Level

VDD-0.4

V

Operating Supply Current

No Load

35

mA

Short-circuit Current

±120

mA

Input Capacitance

OE, Select Pins

5

pF

5. Crystal Specifications

PARAMETERS

SYMBOL

MIN.

TYP.

MAX.

UNITS

Crystal Resonator Frequency

12

24

MHz

Crystal Loading Capacitance Rating

TBD

pF

Driving power

1

mW

ESR

25

Ω