Preliminary

PLL102-109

Programmable DDR Zero Delay Clock Driver

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 02/26/03 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

VDD

3,12,23

PWR

2.5V power supply.

GND

6,15,28

PWR

Ground

AVDD

10

PWR

Analog power supply (2.5V).

AGND

11

PWR

Analog ground.

CLKT(0:5)

2,4,13,17,24,26

OUT

“True” clocks of differential pair outputs.

CLKC(0:5)

1,5,14,16,25,27

OUT

“Complementary” clocks of differential pair outputs.

CLK_INT

8

IN

Single-ended 3.3V tolerant input.

ADDR_SEL

18

IN

If ADDR_SEL=0(default) Write condition (0xD4) or a read condition (0xD5)

If ADDR_SEL=1, Write condition (0xD6) or a read condition (0xD7)

N/C

9,21

-

Not connected.

FB_OUTT

19

OUT

“True” feedback output. Dedicated for external feedback. It switches at the

same frequency as the CLK_INT.

FB_INT

20

IN

“True” feedback input, provides feedback signal to the internal PLL for

synchronization with CLK_INT to eliminate phase error.

SDATA

22

I/O

SCLK

7

IN

Serial data input for serial interface port.

Functionality

INPUTS

OUTPUTS

AVDD

CLK_INT

CLK_INC

CLKT

CLKC

FB_OUTT

PLL State

2.5V (Nom)

L

H

L

H

L

On

2.5V (Nom)

H

L

H

L

H

On

GND

L

H

L

H

L

Bypass/Off

GND

H

L

H

L

H

Bypass/Off