7.

Write Operations

All write operations for the AT24CSW01X/AT24CSW02X begin with the host sending a Start condition, followed by

a device address byte with the R/W bit set to logic ‘0’ and then by the word address byte. The data value(s) to be

written to the device immediately follow the word address byte. When writing to a protected region, the device will

ACK but the internal write cycle will abort, leaving the device ready for the next operation.

7.1

Byte Write

The AT24CSW01X/AT24CSW02X supports the writing of a single 8-bit byte. Selecting a data word in the

AT24CSW01X requires a 7-bit word address, while selecting a data word in the AT24CSW02X requires an 8-bit

word address.

Upon receipt of the proper device address and the word address bytes, the EEPROM will send an ACK. The device

will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will respond

with an ACK. The addressing device, such as a bus client, must then terminate the write operation with a Stop

while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write cycle

and the EEPROM will not respond until the write is complete.

Figure 7-1. Byte Write

SCL

SDA

Device Address Byte

Word Address Byte

Data Word

Start

by

Host

ACK

from

Client

MSb

MSb

Stop

by

Host

MSb

1

2

3

4

5

6

7

8

9

1

0

1

0

#

#

#

0

0

1

2

3

4

5

6

7

8

9

D7 D6 D5 D4 D3 D2 D1 D0

0

A7 A6 A5

A4

A3 A2 A1

A0

0

1

2

3

4

5

6

7

8

9

ACK

from

Client

ACK

from

Client

(1)

Notes: 

1.

The A7 bit falls outside of the addressable 1K range and is therefore a don’t care value on an AT24CSW01x.

2.

# indicates the hardware address value that is managed by the ordering code of the device (see Table 6-2).

7.2

Page Write

A page write operation allows up to 8 bytes to be written in the same write cycle, provided all bytes are in the same

row of the memory array (where address bits A7/A6 to A3 are the same). Partial page writes of less than 8 bytes are

also allowed.

A page write is initiated the same way as a byte write, but the bus host does not send a Stop condition after the first

data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus host can

transmit up to seven additional data words. The EEPROM will respond with an ACK after each data word is received.

Once all data to be written has been sent to the device, the bus host must issue a Stop condition (see Figure 7-2), at

which time the internally self-timed write cycle will begin.

The lower three bits of the word address are internally incremented following the receipt of each data word. The

higher order address bits are not incremented and retain the memory page row location. Page write operations are

limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. When

the incremented word address reaches the page boundary, the address counter will rollover to the beginning of the

same page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could

become unintentionally altered.

AT24CSW01X/AT24CSW02X

Write Operations

and its subsidiaries

Datasheet

DS20006396B-page 18