AS7C33256PFS16A

AS7C33256PFS18A

®

3/14/01; V.1.0

Alliance Semiconductor

P. 10 of 11

Package Dimensions

100-pin quad flat pack (TQFP)

Dimensions in millimeters

TQFP

Min

Max

A1

0.05

0.15

A2

1.35

1.45

b0.22

0.38

c0.09

0.20

D

13.90

14.10

E

19.90

20.10

e

0.65 nominal

Hd

15.90

16.10

He

21.90

22.10

L0.45

0.75

L1

1.00 nominal

α

0°

7°

A1 A2

L1

L

c

He

E

Hd

D

b

e

α

Notes

1) For test conditions, see AC Test Conditions, Figures A, B, C.

2) This parameter measured with output load condition in Figure C.

3) This parameter is sampled, but not 100% tested.

5) tCH measured as HIGH above VIH and tCL measured as LOW below VIL.

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

7) Write refers to

8) Chip select refers to

AC test conditions

351

Ω

5 pF*

317

Ω

GND

Figure C: Output load(B)

*including scope

and jig capacitance

50

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

for 3.3V I/O;

for 2.5V I/O

Thevenin equivalent:

+3.3V for 3.3V I/O;

+2.5V for 2.5V I/O