M69AW024BE

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Table 8. Write Mode AC Characteristics

Note: 1. The maximum value of this timing is applicable if E1 is kept Low without any address change. If needed by system operation, please

contact your local ST representative for relaxation of the 1000ns limitation.

2. Minimum value must be equal to or greater than the sum of the write pulse (

3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.

4. Applicable to Byte Masking only. Byte Masking set-up time is defined from the falling edge of E1 or W whichever occurs last.

5. Applicable to Byte Masking only. Byte Masking hold time is defined from the rising edge of E1 or W whichever occurs first.

6. Write recovery is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.

8. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before

Symbol

Alt.

Parameter

M69AW024BE

Unit

–60

Min

Max

(1,2)

Chip Enable Write Cycle Time

70

1000

ns

(2)

Address Set-up Time to Chip Enable Low

0

ns

(3)

Chip Enable Write Pulse Width

45

ns

(3)

Write Enable Write Pulse Width

45

ns

(3)

LB, UB Pulse (Write Operation)

45

ns

(4)

LB, UB Byte Masking Set-up Time

–5

ns

(5)

LB, UB Hold Time

–5

ns

(6)

Write Recovery Time

0

ns

Chip Enable High Pulse

10

ns

Write Enable High Pulse

10

1000

ns

LB, UB High Pulse

10

1000

ns

Data Set-up Time

15

ns

Data Hold Time

0

ns

(7)

Output Enable High to Chip Enable Low Set-up Time

–5

ns

(8)

Output Enable Set-up Time

0

ns

LB, UB Low to LB, UB High for Page Access

30

ns