ADS5242IPAP datasheet(7/29 Pages) TI

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LVDS DIGITAL DATA AND CLOCK OUTPUTS

SWITCHING CHARACTERISTICS

ADS5242

SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005

Test conditions at IO = 3.5mA, RLOAD = 100Ω, CLOAD = 6pF, and 50% duty cycle. IO refers to the current setting for the LVDS buffer. RLOAD is

the differential load resistance between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between each of the

LVDS pins and ground. CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch

transmission line of 100

Ω characteristic impedance between the device and the load. All LVDS specifications are characterized, but not

parametrically tested at production. LCLKOUT refers to (LCLKP – LCLKN); ADCLKOUT refers to (ADCLKP – ADCLKN); DATA OUT refers to

(OUTP – OUTN); and ADCLK refers to the input sampling clock.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC SPECIFICATIONS(1)

VOH Output Voltage High, OUTP or OUTN

RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8

1265

1365

1465

VOL Output Voltage Low, OUTP or OUTN

RLOAD = 100Ω ± 1%

940

1040

1140

|VOD| Output Differential Voltage

RLOAD = 100Ω ± 1%

275

325

375

VOS Output Offset Voltage(2)

RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8

1.1

1.2

1.3

RO Output Impedance, Differential

Normal Operation

Ω

RO Output Impedance, Differential

Power-Down

Ω

CO Output Capacitance(3)

∆V

OD|

Change in |VOD| Between 0 and 1

RLOAD = 100Ω ± 1%

∆V

Change Between 0 and 1

RLOAD = 100Ω ± 1%

ISOUT Output Short-Circuit Current

Drivers Shorted to Ground

ISOUTNP Output Current

Drivers Shorted Together

DRIVER AC SPECIFICATIONS

ADCLKOUT Clock Duty Cycle(4)

LCLKOUT Duty Cycle(4)

Data Setup Time(5)(6)

0.4

Data Hold Time(7)(6)

0.25

LVDS Outputs Rise/Fall Time(8)

IO = 2.5mA

400

IO = 3.5mA

180

300

500

IO = 4.5mA

230

IO = 6.0mA

180

LCLKOUT Rising Edge to ADCLKOUT Rising Edge(9)

0.37

0.64

0.9

ADCLKOUT Rising Edge to LCLKOUT Falling Edge(9)

0.37

0.64

0.9

ADCLKOUT Rising Edge to DATA OUT Transition(9)

–0.3

+0.3

(1)

The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.

(2)

VOS refers to the common-mode of OUTP and OUTN.

(3)

Output capacitance inside the device, from either OUTP or OUTN to ground.

(4)

Measured between zero crossings.

(5)

DATA OUT (OUTP – OUTN) crossing zero to LCLKOUT (LCLKP – LCLKN) crossing zero.

(6)

Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, as well as effects of clock jitter within

the device.

(7)

LCLKOUT crossing zero to DATA OUT crossing zero.

(8)

Measured from –100mV to +100mV on the differential output for rise time, and +100mV to –100mV for fall time.

(9)

Measured between zero crossings.

TMIN = –40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle,

AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless

otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SWITCHING SPECIFICATIONS

tSAMPLE

15.4

tD(A) Aperture Delay(1)

6.5

Aperture Jitter (uncertainty)

tD(pipeline) Latency

6.5

Cycles

tPROP Propagation Delay(2)

4.8

6.5

(1)

Rising edge of ADCLK to actual instant when data is sampled within the ADC.

(2)

Falling edge of ADCLK to zero-crossing of rising edge of ADCLKOUT.

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