4.12

Port Matrix Control

Port matrix control enables layout designers to ascribe each physical port in the system to a logical port if required.

4.13

Power Good Interrupt

Interrupt from power supply directly to the manager. For systems comprising more than a single power supply, in

case one power supply fails, a port shutdown mechanism is executed to maintain operation and prevent the collapse

of other power supplies.

When a function is used, PGD0, PGD1, PGD2, and PGD3 should be connected to the main power supplies status

indication pin. Any change of at least 1 µs on these lines triggers a pre-defined disconnection matrix. This matrix is

defined by the PSE controller system power parameters. The port shutdown function reacts within 2 µs to any power

good event.

4.14

Power Sequencing

Figure 4-2. Power Sequencing

With an external 5 V and/or 3.3 V supply:

• The maximum 3.3 V slew rate is 100 ms.

• Td2: 5 V should be raised before or at the same time as 3.3 V.

• Td3: 3.3 V should be dropped before or at the same time as 5 V.

For details about PD39208 5 V and 3.3 V power supply connection options, see AN3615 Designing an IEEE

®

802.3af/at PoE System Based on PD39210 + PD39208 Chipset.

4.15

Ground

The digital ground and analog ground should be tied together on the board in a single point only for the entire system.

PD39208

Application Information

Datasheet

DS00003555B-page 17