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RFMD2080

DS140110

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Notes:

1.

An RC low pass filter may be used on this line to reduce digital noise.

2.

If the device is under software control this input can be configured as a general purpose output (GPO).

3.

Connect a 51K

 resistor from this pin to ground. This pin is sensitive to low frequency noise injection.

4.

DC bias voltage and modulation should be applied to this pin.

5.

This pin must be connected to ANA_VDD2 using an RF choke or center tapped transformer (see application schematic).

Pin Names and Descriptions

Pin

Name

Description

1ENBL/GPO5

Device Enable pin (see note 1 and 2).

2

EXT_LO

External local oscillator input. Use AC coupling capacitor.

3

EXT_LO_DEC

Decoupling pin for external local oscillator. Use AC coupling capacitor.

4REXT

External bandgap bias resistor (see note 3).

5

ANA_VDD1

Analog supply. Use good RF decoupling.

6LFILT1

Phase detector output. Low-frequency noise-sensitive node.

7LFILT2

Loop filter op-amp output. Low-frequency noise-sensitive node.

8LFILT3

VCO control input. Low-frequency noise-sensitive node.

9

MODE/GPO6

Mode select pin (see notes 1 and 2).

10

REF_IN

Reference input. Use AC coupling capacitor.

11

NC

12

TM

Connect to ground.

13

RF_OUT_N

Differential output (see note 5).

14

RF_OUT_P

Differential output (see note 5).

15

GPO1/ADD1

General purpose output / MultiSlice address bit.

16

GPO2/ADD2

General purpose output / MultiSlice address bit.

17

DIG_VDD

Digital supply. Should be decoupled as close to the pin as possible.

18

MOD_Q_N

Modulator Q differential input (see note 4).

19

MOD_Q_P

Modulator Q differential input (see note 4).

20

NC

21

NC

22

MOD_I_N

Modulator I differential input (see note 4).

23

MOD_I_P

Modulator I differential input (see note 4).

24

ANA_VDD2

Analog supply. Use good RF decoupling.

25

GPO3

General purpose output

26

GPO4/LD/DO

General purpose output / Lock detect output / serial data out.

27

NC

28

NC

29

RESETX

Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.

30

ENX

Serial interface select (active low) (See note 1).

31

SCLK

Serial interface clock (See note 1).

32

SDATA

Serial interface data (See note 1).

Exposed Paddles

Ground reference, should be connected to PCB ground through a low impedance path.