OR3C55-5BA352I datasheet(44/210 Pages) AGERE

44 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Input/Output Cells

(continued)

PIC Routing Resources

The PIC routing borrows many of the concepts and

constructs from the PLC routing. It is designed to be

able to gather an 8-bit bidirectional bus from any eight

consecutive I/O pads and route them to either or both

of the two adjacent PLCs. The eight I/O bits do not

need to start at a PIC boundary; that is, they may start

at one of the middle two PIOs in a PIC and span three

PICs.

Substantial routing has been added to the PIC to off-

load PLC routing from being used to move signals

around the PLC array perimeter. This saves PLC rout-

ing for logic purposes and provides greater flexibility for

locking design pinouts prior to final placement and rout-

ing of the device, or allowing a change in the pinout late

in the design cycle. The PIC routing has also been

increased substantially to allow routing to the complex

PIO cells that now allow multiple inputs and outputs per

device pin, along with new sequential control signals,

such as clock enable, LSR, and clock.

PICs are grouped in pairs for purposes of discussing

PIC routing. On the sides of a device, the PICs in a pair

are referred to as top and bottom. On the top or bottom

of a device, the PICs in a pair are referred to as left or

right. For example, on the top edge of the device, the

leftmost PIC, PT1, is the left PIC of a pair, and PIC PT2

is the right PIC of that pair. The next PIC to the right,

PT3, is the left PIC of the next pair, and so on.

The need for PIC pairs stems from the routing of

switching segments and PLC half- and long-line driv-

ers. As described below, the connectivity for these

types of routing is grouped across pairs of PICs to pro-

vide complete and fast routing of I/O signals between a

given PIC and the three adjacent PLCs: one orthogonal

and two diagonal.

PIC routing segments use the same terminology as

PLC routing segments, but are prefixed with a p to dis-

tinguish them as belonging to the PICs.

PIC Switching Segments. Each PIC has two groups

of switching segments (pSW), each group having eight

lines with connectivity to the PIOs in groups of four.

One set of switching segments connects to the PIC to

the left (above), and the other set connects to the

switching segments of the PIC to the right (below). This

means of connectivity between PICs using staggered

connections of groups of switching segments allows a

given PIC to route signals to both adjacent PICs and all

adjacent PLCs efficiently. This provides single signal

routing flexibility and routing of multiple buses on

groups of I/Os without tying up global routing

resources.

px1 Routing Segments. There are five px1 routing

segments in each PIC that run parallel to the edge of

the chip on which the PIC resides, each broken by a

CIP in each PIC. The px1 segments have connectivity

to the pSW segments and to the x1 routing segments

of the two adjacent PLCs.

px2 Routing Segments. There are five px2 routing

segments in each PIC that run parallel to the edge of

the chip on which the PIC resides. To provide greater

routing flexibility, the CIPs that break the px2 segments

every two PICs are staggered across the two PICs in a

pair. One PIC of the pair has break CIPs on the even-

numbered px2 segments, and the other has them on

the odd-numbered px2 segments. The px2 segments

have connectivity to the pSW segments and to the x1

routing segments of the two adjacent PLCs.

px5 Routing Segments. There are ten px5 routing

segments in each PIC that run parallel to the edge of

the chip on which the PIC resides. Two of the ten seg-

ments are broken in each PIC so that each segment is

broken every five PICs. All ten px5 segments break at

the corners of the chip, allowing independent px5 rout-

ing on each edge of the chip. The px5 routing seg-

ments connect to the pSW segments and the x5 and

xH routing segments of the two adjacent PLCs.

pxH Routing Segments. Each PIC contains eight pxH

routing segments that run parallel to the edge of the

chip on which the PIC resides. The pxH segments have

connectivity with the xL, xH, and one set of xBID rout-

ing segments in the immediately adjacent PLC.

pxL Routing Segments. There are ten pxL routing

segments in each PIC that run parallel to the edge of

the chip on which the PIC resides. Each of the xL lines

makes a connection to an xL line from the adjacent

PLC. PIC long lines (xL) can be used for global signal

distribution just as PLC xL lines can.

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