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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC885CZP66 датащи(PDF) 36 Page - NXP Semiconductors |
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MPC885CZP66 датащи(HTML) 36 Page - NXP Semiconductors |
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36 / 87 page  MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 36 Freescale Semiconductor Bus Signal Timing Table 10 provides the interrupt timing for the MPC885/MPC880. Figure 26 provides the interrupt detection timing for the external level-sensitive lines. Figure 26. Interrupt Detection Timing for External Level Sensitive Lines Figure 27 provides the interrupt detection timing for the external edge-sensitive lines. Figure 27. Interrupt Detection Timing for External Edge Sensitive Lines Table 10. Interrupt Timing Num Characteristic1 1 The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC885/MPC880 is able to support. All Frequencies Unit Min Max I39 IRQx valid to CLKOUT rising edge (setup time) 6.00 ns I40 IRQx hold time after CLKOUT 2.00 ns I41 IRQx pulse width low 3.00 ns I42 IRQx pulse width high 3.00 ns I43 IRQx edge-to-edge time 4 × TCLOCKOUT — CLKOUT IRQx I39 I40 CLKOUT IRQx I41 I42 I43 I43 |
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