ACE25QC160GLFMLTH datasheet(32/73 Pages) ACE

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ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around”

The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a

“Set Burst with Wrap” (77H) instruction prior to EBH. The “Set Burst with Wrap” (77H) instruction can either

enable or disable the “Wrap Around” feature for the following EBH instructions. When “Wrap Around” is

enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte

page. The output data starts at the initial address specified in the instruction, once it reaches the ending

boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary

automatically until /CS is pulled high to terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then

fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read

instructions.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable

or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around

section within a page.

Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read instruction is similar to the Quad Fast Read instruction except that the

lowest address bit (A0) must equal 0 and 2-dummy clock. The instruction sequence is shown in the

followed Figure 15 the first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of

Status Register (S9) must be set to enable for the Quad I/O Word Fast Read instruction.

Quad I/O Word Fast Read with “Continuous Read Mode”

The Quad I/O Word Fast Read instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input 3-byte Address bits (A23-0). If the “Continuous Read

Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read instruction (after /CS is raised and then

lowered) does not require the E7H instruction code, the instruction sequence is shown in the followed

Figure 16. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction requires the

first E7H instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset command

can also be used to reset (M5-4) before issuing normal command.

Figure15. Quad I/O Word Fast Read Sequence Diagram (Initial command or previous (M5-

4)≠

(1,0),SPI mode only)

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