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UPD16686 датащи(PDF) 21 Page - NEC |
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UPD16686 датащи(HTML) 21 Page - NEC |
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21 / 99 page ![]() Data Sheet S15548EJ1V0DS 21 µµµµPD16686, 16687 (1) i80 series parallel interface When i80 series parallel data transfer has been selected, data is written to the µ PD16686, 16687 at the rising edge of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 3-1. i80 Series Interface Data Bus Status /CS1 (CS2=H) /WR /RD DBn Hi-Z Hi-Z Data write Data Read Valid data (2) M68 series parallel interface When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H, outputs valid data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the R,/W signal (R,/W = L) Figure 3-2. M68 Series Interface Data Bus Status /CS1 (CS2=H) R,/W E DBn Hi-Z Hi-Z Valid data Invalid data |
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