8 Detailed Description

8.1 Overview

The SN74HCS138 is a high speed silicon gate CMOS decoder well suited to memory address decoding or data

routing applications. It contains a single 3:8 decoder. All inputs include Schmitt-triggers allowing for slow input

transitions and providing additional noise margin.

eight decoder.

any input strobe is active, all outputs are forced into the high state.

The demultiplexing function is accomplished by first using the select inputs to choose the desired output, and

then using one of the strobe inputs as the data input.

The outputs for the SN74HCS138 are normally high, and low when selected.

8.2 Functional Block Diagram

A

0

A

1

A

2

OUTPUT

ENABLE

Y

0

Y

1

Y

2

G

1

G

2

Y

3

Y

4

Y

5

Y

6

Y

7

G

0

3:8 DECODER

000

001

010

011

100

101

110

111

Figure 8-1. Logic Diagram (Positive Logic) for the SN74HCS138

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are

typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table

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SN74HCS138

SCLS832B – OCTOBER 2020 – REVISED MAY 2021

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Product Folder Links: SN74HCS138