CY29976
Document #: 38-07413 Rev. *A
Page 4 of 10
Z
ero Delay Buffer
When used as a zero delay buffer the CY29976 will likely be
in a nested clock tree application. For these applications the
CY29976 offers a low voltage PECL clock input as a PLL ref-
erence. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The CY29976 then can lock onto the
LVPECL reference and translate with near zero delay to low
skew outputs.
By using one of the outputs as a feedback to the PLL the prop-
agation delay through the device is eliminated. The PLL works
to align the output edge with the input reference edge thus
producing a near zero delay. The reference frequency affects
the static phase offset of the PLL and thus the relative delay
between the inputs and outputs. Because the static phase off-
set is a function of the reference clock the Tpd of the CY29976
is a function of the configuration used.
Glitch-Free Output Frequency Transitions
Customarily when output buffers have their internal counter’s
changed “on the fly’ their output clock periods will:
• Contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequency that is being transitioned to.
• Contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency that is being transitioned to.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
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