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ACE25AA160GFMLTH датащи(PDF) 13 Page - ACE Technology Co., LTD. |
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ACE25AA160GFMLTH датащи(HTML) 13 Page - ACE Technology Co., LTD. |
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13 / 46 page ![]() ACE25AA160G Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase VER 1.2 13 6. Quad I/O Word Fast Read Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Quad I/O Word Fast Read Data: the lowest address bit must be 0 8. Security Registers Address : Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address; Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address; Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address; Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address. ID Definitions Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH 0B 40 15 90H 0B 14 ABH 14 Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low→sending the Write Enable command→CS# goes high. Figure1. Write Enable Sequence Diagram |
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