ACE25AA400G datasheet(21/49 Pages) ACE

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ACE25AA400G

Serial NOR Flash Memory 4M bits 3.0V Quad I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.3

Quad Page Program (QPP) (32H)

The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and

IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write

Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit

before sending the Page Program command. The Quad Page Program command is entered by driving

CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO

pins.

The command sequence is shown in Figure 17. If more than 256 bytes are sent to the device, previously

latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within

the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the

requested ad- dresses without having any effects on the other bytes of the same page. CS# must be

driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page

Program command is not executed.

As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is

initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check

the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed

Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

A Quad Page Program command applied to a page which is protected by the Block Protect (BP3, BP2,

BP1, BP0) will not be executed.

Figure17. Quad Page Program Sequence Diagram

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