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ACE24AC08C датащи(PDF) 3 Page - ACE Technology Co., LTD. |
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ACE24AC08C датащи(HTML) 3 Page - ACE Technology Co., LTD. |
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3 / 20 page ![]() ACE24AC08C Two-wire Serial EEPROM VER 1.1 3 Block Diagram Pin Description A. SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. B. SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired- OR with other open-drain output devices. C. DEVICE / CHIP SELECT ADDRESSES (A2) This is the chip select input signal for the serial EEPROM devices. Typically, this signal is hardwired to either VIH or VIL. If left unconnected, it is internally recognized as VIL. However, due to capacitive coupling that may appear in customer applications, ACE recommends always connecting the address pin to a known state. When using a pull-up or pull-down resistor, ACE recommends using 10kΩ or less. D. WRITE PROTECT (WP) The ACE24AC08C devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level. If left unconnected, it is internally recognized as VIL. However, due to capacitive coupling that may appear in customer applications, ACE recommends always connecting the WP pin to a known state. When using a pull-up or pull- down resistor, ACE recommends using 10kΩ or less. |
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