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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCMD3140IRTER датащи(PDF) 83 Page - Texas Instruments |
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PCMD3140IRTER датащи(HTML) 83 Page - Texas Instruments |
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83 / 106 page  Table 7-95. VAD_CFG1 Register Field Descriptions (continued) Bit Field Type Reset Description 5-4 VAD_CH_SEL[1:0] R/W 10b VAD channel select. 0d = Channel 1 is monitored for VAD activity 1d = Channel 2 is monitored for VAD activity 2d = Channel 3 is monitored for VAD activity 3d = Channel 4 is monitored for VAD activity 3-2 VAD_CLK_CFG[1:0] R/W 00b Clock select for VAD 0d = VAD processing using internal oscillator clock 1d = VAD processing using external clock on BCLK input 2d = VAD processing using external clock on MCLK input 3d = Custom clock configuration based on MST_CFG, CLK_SRC and CLKGEN_CFG registers in page 0 1-0 VAD_EXT_CLK_CFG[1:0] R/W 00b Clock configuration using external clock for VAD. 0d = External clock is 3.072 MHz 1d = External clock is 6.144 MHz 2d = External clock is 12.288 MHz 3d = External clock is 18.432 MHz 7.6.2.3 VAD_CFG2 Register (Address = 0x1F) [Reset = 0x8] VAD_CFG2 is shown in Figure 7-118 and described in Table 7-96. Return to the Table 7-93. This register is configuration register 2 for voice activity detection. Figure 7-118. VAD_CFG2 Register 7 6 5 4 3 2 1 0 RESERVED SDOUT_INT_C FG RESERVED RESERVED VAD_PD_DET_ EN RESERVED R/W-0b R/W-0b R-0b R/W-0b R/W-1b R-000b Table 7-96. VAD_CFG2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0b Reserved bit; Write only reset value 6 SDOUT_INT_CFG R/W 0b SDOUT interrupt configuration. 0d = SDOUT pin is not enabled for interrupt function 1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded 5 RESERVED R 0b Reserved bit; Write only reset value 4 RESERVED R/W 0b Reserved bit; Write only reset value 3 VAD_PD_DET_EN R/W 1b Enable ASI output data during VAD activity. 0d = VAD processing is not enabled during ADC recording 1d = VAD processing is enabled during ADC recording and VAD interrupts are generated as configured 2-0 RESERVED R 000b Reserved bits; Write only reset values www.ti.com PCMD3140 SBASA64A – DECEMBER 2020 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: PCMD3140 |
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