LPC82X datasheet(13/83 Pages) NXP

13 / 83 page

LPC82x

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Product data sheet

Rev. 1.4 — 19 March 2021

13 of 82

NXP Semiconductors

LPC82x

32-bit ARM Cortex-M0+ microcontroller

8.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight

coupling to the CPU allows for low interrupt latency and efficient processing of late arriving

interrupts.

8.6.1 Features

• Nested Vectored Interrupt Controller is a part of the ARM Cortex-M0+.

Fig 6.

LPC82x Memory mapping

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 0000

0x4005 8000

0x4005 C000

0x4006 0000

0x4006 4000

0x4006 8000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

MRT

reserved

12-bit ADC

self wake-up timer

reserved

WWDT

analog comparator

PMU

30 - 31 reserved

0x4002 C000

0x4003 0000

0x4003 4000

DMA TRIGMUX

input mux

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1FFF 0000

0x1FFF 3000

0x2000 0000

0x5000 0000

0x5000 4000

0xFFFF FFFF

reserved

0x4000 0000

0x4008 0000

APB peripherals

CRC

0x5000 8000

SCTimer/PWM

0x5000 C000

0xA000 0000

GPIO

0xA000 4000

0xA000 8000

GPIO PINT

0x1000 1000

4 KB SRAM0

0x1001 2000

4 KB SRAM1

0x1000 0000

LPC82x

0x0000 8000

32 KB on-chip flash

12 KB boot ROM

0x1400 0000

0x1400 1000

4 KB MTB registers

0x0000 0000

0x0000 00C0

active interrupt vectors

reserved

DMA

reserved

flash controller

SPI0

reserved

switch matrix

IOCON

system control (SYSCON)

reserved

0x4005 4000

I2C0

I2C1

SPI1

reserved

0x4006 C000

0x4007 0000

USART0

USART1

USART2

0x4007 4000

I2C2

0x4007 8000

I2C3

reserved

0xE000 0000

0xE010 0000

private peripheral bus

aaa-015072

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