MCP48FVB08 datasheet(57/112 Pages) MICROCHIP

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DS20006362A-page 57

MCP48FXBX4/8

4.2.6

WIPERLOCK TECHNOLOGY

The MCP48FXBX4/8 WiperLock technology allows

application-specific device settings (DAC register and

configuration) to be secured without requiring the use

of an additional write-protect pin. There are two Con-

figuration bits (DLn:CLn) for each DAC channel (DAC0

through DAC7).

Dependent on the state of the DLn:CLn Configuration

bits, WiperLock technology prevents the serial com-

mands from the following actions on the DACn

registers and bits:

• Writing to the specified volatile DACn register

memory location

• Writing to the specified nonvolatile DACn register

memory location

• Writing to the specified volatile DACn

Configuration bits

• Writing to the specified nonvolatile DACn

Configuration bits

Each pair of these Configuration bits controls one of

the four modes.

To modify the Configuration bits, the HVC pin must be

forced to the VIHH state and then an enable or disable

command must be received for the desired pair of

DAC register addresses.

4.2.6.1

POR/BOR Operation with

WiperLock Technology Enabled

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the volatile

DACn register values with the nonvolatile or default

factory values (in case of volatile memory only devices).

Example: To modify the CL0 bit, the enable or disable

command specifies address 00h; while to modify the

DL0 bit, the enable or disable command specifies

address 10h.

Note:

During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, the MCP48FXBX4/8 will com-

mand error that command byte. To reset

the serial interface state machine, the CS

pin must be driven to the Inactive state

(VIH) before returning to the Active state

(VIL or VIHH).

TABLE 4-3:

WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS – FUNCTIONAL DESCRIPTION

DLn:CLn(1)

Comments

DACn Wiper

DACn Configuration(1)

Volatile

Nonvolatile

Volatile

Nonvolatile

Locked

All DACn registers are locked.

Locked

Unlocked

Locked

All DACn registers are locked, except for volatile

DACn Configuration registers. This allows

operation of Power-Down modes.

Unlocked

Locked

Unlocked

Locked

Volatile DACn registers are unlocked, nonvolatile

DACn registers are locked.

Unlocked

All DACn registers are unlocked.

Note 1:

The state of these Configuration bits (DLn:CLn) is reflected in the WLnB:WLnA bits, as shown in

Control bits (PDnB:PDnA) and Output Gain bits (Gx).

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