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CY28159
Document #: 38-07118 Rev. **
Page 10 of 13
Sample Layout
FB
+3.3V Supply
FB
C1
C2
0.005
µF
10
µF
0.005
µF
G
G
G
G
VDDQ3A
*
VDDQ3
C3
48
47
46
45
44
43
42
41
40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
G
V
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Cermaic Caps C1 & C3 = 10–22 µF
C2 & C4 = 0.005 µF
FB = Dale ILB1206 - 300 (300
Ω @ 100 MHz)
All bypass caps = 0.1
µF cermamic. Low ESR
G
V
G
V
G
V
G
V
G
V
G
V
G
V
G
V
*
*
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G