9

LT1672/LT1673/LT1674

diverting the current from diff amp Q1-Q2 to current

mirror Q8-Q9. The current from Q8 biases on the other

diff amp consisting of PNP’s Q5-Q6 and NPN’s Q3-Q4.

Though Q5-Q6 are driven from the emitters rather than

the base, the basic diff amp action is the same. When the

devices Q3 and Q4 act as followers, forming a buffer

between the amplifier inputs and the emitters of the Q5-

Schottky diodes D1 and D2 reverse bias and devices Q3

and Q4 then act as diodes. The diff amp formed by Q5-Q6

operates normally, however, the input bias current in-

creases to the emitter current of Q5-Q6, which is typically

180nA. The graph, Input Bias Current vs Common Mode

Voltage found in the Typical Performance Characteristics

section, shows these transitions at three temperatures.

The collector currents of the two-input pairs are combined

in the second stage consisting of Q11 to Q16, which

furnishes most of the voltage gain. Capacitor C1 sets the

amplifier bandwidth. The output stage is configured for

maximum swing by the use of common emitter output

devices Q21 and Q22. Diodes D4 to D6 and current source

Q15 set the output quiescent current.

Figure 3. Simplified Schematic

1672/3/4 F03

Q6

Q4

Q16

Q17

Q19

Q18

Q22

C1

D1

D2

D3

Q3

Q11

Q2

Q7

Q10

Q13

Q20

Q21

OUT

Q12

Q14

Q15

Q5

Q8

R1

R2

+

D6

D5

D4

D7

Q9

Q1

APPLICATIO S I FOR ATIO

The device will not be damaged if the inputs are taken lower

than 300mV below the negative supply as long as the cur-

rent out of the pin is limited to less than 10mA. However,

the output phase is not guaranteed and the supply current

will increase.

Output

The graph, Capacitive Load Handling, shows amplifier sta-

bility with the output biased at half supply. If the output is

to be operated within about 100mV of the positive rail, the

allowable load capacitance is less. With this output volt-

the load capacitance should be less than 500pF with a 5V

supply and less than 100pF with a 30V supply.

Rail-to-Rail Operation

The simplified schematic, Figure 3, details the circuit

design approach of the LT1672/LT1673/LT1674. The

amplifier topology is a three-stage design consisting of a

rail-to-rail input stage, that continues to operate with the

inputs above the positive rail, a folded cascode second

stage that develops most of the voltage gain, and a rail-to-

rail common emitter stage that provides the current gain.

The input stage is formed by two diff amps Q1-Q2 and Q3-