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MCP48FEB02 датащи(PDF) 31 Page - Microchip Technology

номер детали MCP48FEB02
подробное описание детали  8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile Digital-to-Analog Converters with SPI Interface
PDF  92 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
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MCP48FEB02 датащи(HTML) 31 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS20005429B-page 31
MCP48FEBXX
4.2
Device Memory
User memory includes three types of memory:
• Volatile Register Memory (RAM)
• Nonvolatile Register Memory
• Device Configuration Memory
Each memory address is 16 bits wide. There are five
nonvolatile user-control bits that do not reside in
memory mapped register space (see Section 4.2.3
“Device Configuration Memory”
).
4.2.1
VOLATILE REGISTER MEMORY
(RAM)
There are up to six volatile memory locations:
• DAC0 and DAC1 Output Value Registers
• VREF Select Register
• Power-Down Configuration Register
• Gain and Status Register
• WiperLock Technology Status Register
The volatile memory starts functioning when the
device VDD is at (or above) the RAM retention voltage
(VRAM). The volatile memory will be loaded with the
default device values when the VDD rises across the
VPOR/VBOR voltage trip point.
4.2.2
NONVOLATILE REGISTER
MEMORY
This memory can be grouped into two uses of
nonvolatile memory. These are the DAC Output Value
and Configuration registers:
• Nonvolatile DAC0 and DAC1 Output Value
Registers
• Nonvolatile VREF Select Register
• Nonvolatile Power-Down Configuration Register
• Nonvolatile Gain Register
The nonvolatile memory starts functioning below the
device’s VPOR/VBOR trip point, and is loaded into the
corresponding volatile registers whenever the device
rises above the POR/BOR voltage trip point.
The device starts writing the EEPROM memory
location at the completion of the serial interface
command. For the SPI interface, this is when the CS
pin goes inactive (VIH).
The nonvolatile DAC registers enable stand-alone
operation of the device (without Microcontroller control)
after being programmed to the desired value.
Note:
When the nonvolatile memory is written,
the corresponding volatile memory is not
modified.
TABLE 4-1:
MEMORY MAP (x16)
Function
Function
00h Volatile DAC0 Register
CL0
10h Nonvolatile DAC0 Register
DL0
01h Volatile DAC1 Register
CL1
11h
Nonvolatile DAC1 Register
DL1
02h Reserved
—
12h Reserved
—
03h Reserved
—
13h Reserved
—
04h Reserved
—
14h Reserved
—
05h Reserved
—
15h Reserved
—
06h Reserved
—
16h Reserved
—
07h Reserved
—
17h Reserved
—
08h VREF Register
—
18h Nonvolatile VREF Register
—
09h Power-Down Register
—
19h Nonvolatile Power-Down Register
—
0Ah Gain and Status Register
—
1Ah NV Gain Register
—
0Bh WiperLock™ Technology Status Register
—
1Bh Reserved
—
0Ch Reserved
—
1Ch Reserved
—
0Dh Reserved
—
1Dh Reserved
—
0Eh Reserved
—
1Eh Reserved
—
0Fh Reserved
—
1Fh Reserved
—
Volatile Memory address range
Nonvolatile Memory address range
Note 1:
Device Configuration Memory bits require a High-Voltage enable or disable command (LAT/LAT0 = VIHH,
or CS = VIHH) to modify the bit value.



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