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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP47FVB01A0T-E/ST датащи(PDF) 20 Page - Microchip Technology |
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MCP47FVB01A0T-E/ST датащи(HTML) 20 Page - Microchip Technology |
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20 / 92 page  MCP47FVBXX DS20005405A-page 20 2015 Microchip Technology Inc. TABLE 1-3: I2C BUS START/STOP BITS AND LAT REQUIREMENTS I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 C TA +125C (Extended) Operating Voltage range is described in DC Characteristics Param. No. Symbol Characteristic Min. Max. Units Conditions FSCL Standard Mode 0 100 kHz Cb = 400 pF, 1.8V - 5.5V(2) Fast Mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V High-Speed 1.7 0 1.7 MHz Cb = 400 pF, 4.5V - 5.5V High-Speed 3.4 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V D102 Cb Bus Capacitive Loading 100 kHz mode — 400 pF 400 kHz mode — 400 pF 1.7 MHz mode — 400 pF 3.4 MHz mode — 100 pF 90 TSU:STA Start Condition Setup Time (Only relevant for repeated Start condition) 100 kHz mode 4700 — ns Note 2 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 91 THD:STA Start Condition Hold time (After this period the first clock pulse is generated) 100 kHz mode 4000 — ns Note 2 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4000 — ns Note 2 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 93 THD:STO Stop Condition Hold Time 100 kHz mode 4000 — ns Note 2 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 94 TLATSU LAT ↑ to SCL↑ (write data ACK bit) Setup Time 10 — ns Write Data delayed(3) 95 TLATHD SCL ↑ to LAT↑ (write data ACK bit) Hold Time 250 — ns Write Data delayed(3) 96 TLAT LAT High or Low Time 50 — ns 97 THVCSU HVC High to SCL High (of Start condition) – Setup Time 25 — µs High-Voltage Commands 98 THVCHD SCL Low (of Stop condition) to HVC Low – Hold Time 25 — µs High-Voltage Commands Note 2 Not Tested. This parameter ensured by characterization. Note 3 The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge (Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not. |
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